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SN65LBC180A Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LBC180A Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page SN65LBC180A, SN75LBC180A LOW POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS SLLS378C − MAY 2000 − REVISED JUNE 2002 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT + Positive-going input threshold voltage IO = − 8 mA 0.2 V VIT − Negative-going input threshold voltage IO = 8 mA − 0.2 V Vhys Hysteresis voltage ( VIT + − VIT −) 50 mV VIK Enable-input clamp voltage II = − 18 mA − 1.5 − 0.8 V VOH High-level output voltage VID = 200 mV, IOH = − 8 mA 4 4.9 V VOL Low-level output voltage VID = − 200 mV, IOL = 8 mA 0.1 0.8 V IOZ High-impedance-state output current VO = 0 V to VCC −1 1 µA IIH High-level enable-input current VIH = 2.4 V − 100 µA IIL Low-level enable-input current VIL = 0.4 V − 100 µA VI = 12 V, VCC = 5 V 0.4 1 II Bus input current VI = 12 V, VCC = 0 V Other input at 0 V 0.5 1 mA II Bus input current VI = − 7 V, VCC = 5 V Other input at 0 V − 0.8 − 0.4 mA VI = − 7 V, VCC = 0 V − 0.8 − 0.3 VI = 0 or VCC, Receiver enabled and driver disabled 4.5 7.5 ICC Supply current VI = 0 or VCC, No load Receiver disabled and driver disabled 0.5 1 mA ICC Supply current No load Receiver enabled and driver enabled 8.5 15 mA † All typical values are at VCC = 5 V and TA = 25°C. receiver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output 7 13 20 ns tPHL Propagation delay time, high- to low-level output VID = −1.5 V to 1.5 V, See Figure 7 7 13 20 ns tsk(p) Pulse skew ( tPHL − tPLH) VID = −1.5 V to 1.5 V, See Figure 7 0.5 1.5 ns tr Output signal rise time See Figure 7 2.1 3.3 ns tf Output signal fall time See Figure 7 2.1 3.3 ns tPZH Output enable time to high level 30 45 ns tPZL Output enable time to low level CL = 10 pF, See Figure 8 30 45 ns tPHZ Output disable time from high level CL = 10 pF, See Figure 8 20 40 ns tPLZ Output disable time from low level 20 40 ns |
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