K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E

CMOS SRAM

PRELIMINARY

Rev 3.0

- 5 -

March 2000

WRITE CYCLE*

* The above parameters are also guaranteed at extended and industrial temperature range.

Parameter

Symbol

K6R4004C1C-10

K6R4004C1C-12

K6R4004C1C-15

K6R4004C1C-20

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Write Cycle Time

10

-

12

-

15

-

20

-

ns

Chip Select to End of Write

7

-

8

-

10

-

12

-

ns

Address Set-up Time

0

-

0

-

0

-

0

-

ns

Address Valid to End of Write

7

-

8

-

10

-

12

-

ns

Write Pulse Width(OE High)

7

-

8

-

10

-

12

-

ns

Write Pulse Width(OE Low)

10

-

12

-

15

-

20

-

ns

Write Recovery Time

0

-

0

-

0

-

0

-

ns

Write to Output High-Z

0

5

0

6

0

7

0

9

ns

Data to Write Time Overlap

5

-

6

-

7

-

9

-

ns

Data Hold from Write Time

0

-

0

-

0

-

0

-

ns

End Write to Output Low-Z

3

-

3

-

3

-

3

-

ns

Address

Data Out

Previous Valid Data

Valid Data

TIMMING DIAGRAMS

CS

Address

OE

Data out

50%

50%

Current

Valid Data

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

levels.

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.