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IS41LV16100A Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS41LV16100A Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
6 / 22 page IS41LV16100A 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 03/02/05 ISSI® ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Max. Unit IIL Input Leakage Current Any input 0V ≤ VIN ≤ VDD –10 10 µA Other inputs not under test = 0V IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA 0V ≤ VOUT ≤ VDD VOH Output High Voltage Level IOH = –2.0 mA (3.3V) 2.4 — V VOL Output Low Voltage Level IOL = 2.0 mA (3.3V) — 0.4 V ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commercial 3.3V — 3 mA Industrial 3.3V — 4 mA ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VDD – 0.2V 3.3V — 2 mA ICC3 Operating Current: RAS, LCAS, UCAS, -50 — 180 mA Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -60 — 170 Average Power Supply Current ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -50 — 180 mA EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -60 — 170 Average Power Supply Current ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 — 180 mA RAS-Only(2,3) tRC = tRC (min.) -60 — 170 Average Power Supply Current ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -50 — 180 mA CBR(2,3,5) tRC = tRC (min.) -60 — 170 Average Power Supply Current Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. |
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