PULSUS

PS9604

Copyright © Pulsus Technologies Inc. 2000

4

AUGUST 2000 REV0.4

Pin Descriptions

PIN No.

PIN NAME

I/O

DESCRIPTION

1

-

Digital Power, +3.3V

2

BCLK

IN

Bit clock input for serial audio data.

BCLK shifts data input on the rising clock edge. Need not run continuously;

may be gated or used in a burst fashion.

This input is 5V tolerant.

3

WCLK

IN

Word clock input for serial audio data.

WCLK latch the shifted data input on the falling clock edge.

This input is 5V tolerant.

4

LDATA

IN

Left channel serial data input.

This input is 5V tolerant.

5

RDATA

IN

Right channel serial data input.

Both LDATA and RDATA are assumed to be MSB-first 2’s-compliment.

If data is absent or held to a constant value (all 0’s or constant values for

8192 words at 44.1/48kHz sampling rate), or any of the input clocks are

removed, an internal MUTE is activated.

This input is 5V tolerant.

6

SF1

OUT

7

SF0

OUT

Sampling rate indication output.

(SF1, SF0) = (0,0) : 44.1kHz

(0,1) : other sampling rate

(1,0) : 48kHz

(1,1) : 32kHz

8

96K

OUT

88.2/96kHz sampling rate indication output.

This pin goes High when the sampling rate is 88.2/96kHz.

9

192K

OUT

176.4/192kHz sampling rate indication output.

This pin goes High when the sampling rate is 176.4/192kHz.

10

FS_CLK

IN

Sampling rate clock input.

This input is 5V tolerant. Internal pull-down resistor.

11

REF_CLK

IN

Reference clock input.

12.288MHz Reference clock is required to detect sampling rate.

This input is 5V tolerant. Internal pull-down resistor.

12

TEST_ENA

-

Chip test mode enabling input.

This pin should be tied to GND for normal operation.

13

SYS_CLK

IN

Master system clock input. Connect to an external clock source.

2048Fs at 32/44.1/48kHz sampling rate,

1024Fs at 88.2/96kHz sampling rate,

512Fs at 176.4/192kHz sampling rate.

This input is 5V tolerant.

14

-

Digital Ground

15

-

Digital Ground

16

PWM_L+

OUT

Left channel Positive PWM output.

17

PWM_L-

OUT

Left channel Negative PWM output.