CY28410
Document #: 38-07593 Rev. *C
Page 2 of 18
Pin Definitions
Pin No.
Name
Type
Description
44,43,41,40
CPUT/C
O, DIF Differential CPU clock outputs.
36,35
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
O, DIF Selectable Differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
14,15
DOT96T, DOT96C
O, DIF Fixed 96-MHz clock output.
18
FS_A
I
3.3V tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
16
FS_B/TEST_MODE
I
3.3V tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z,1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
53
FS_C/TEST_SEL
I
3.3V tolerant input for CPU frequency selection. Selects test mode if pulled
to VIHFS_C when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
39
IREF
I
A Precision resistor is attached to this pin, which is connected to the internal
current reference.
54,55,56,3,4,5 PCI
O, SE 33-MHz clocks.
9,10
PCIF
O, SE 33-MHz clocks.
8
PCIF0/ITP_EN
I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
52
REF
O, SE Reference clock. 3.3V 14.318 MHz clock output.
46
SCLK
I
SMBus-compatible SCLOCK.
47
SDATA
I/O
SMBus-compatible SDATA.
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. recommended output for SATA.
19,20,22,23,2
4,25,31,30,33,
32
SRCT/C
O, DIF Differential serial reference clocks.
12
USB_48
I/O, SE Fixed 48 MHz clock output.
11
VDD_48
PWR 3.3V power supply for outputs.
42
VDD_CPU
PWR 3.3V power supply for outputs.
1,7
VDD_PCI
PWR 3.3V power supply for outputs.
48
VDD_REF
PWR 3.3V power supply for outputs.
21,28,34
VDD_SRC
PWR 3.3V power supply for outputs.
37
VDDA
PWR 3.3V power supply for PLL.
13
VSS_48
GND Ground for outputs.
45
VSS_CPU
GND Ground for outputs.
2,6
VSS_PCI
GND Ground for outputs.
51
VSS_REF
GND Ground for outputs.
29
VSS_SRC
GND Ground for outputs.
38
VSSA
GND Ground for PLL.
17
VTT_PWRGD#/PD
I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a realtime input for asserting
power-down (active high)
50
XIN
I
14.318-MHz Crystal Input
49
XOUT
O, SE 14.318-MHz Crystal Output
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