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EDR2518ABSE-AE Datasheet(PDF) 4 Page - Elpida Memory |
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EDR2518ABSE-AE Datasheet(HTML) 4 Page - Elpida Memory |
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4 / 79 page  Preliminary Data Sheet E0260E40 (Ver. 4.0) 4 EDR2518ABSE Pin Description Signal Input / Output Type #pins Description SIO0, SIO1 Input / Output CMOS Note1 2 Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. CMD Input CMOS Note1 1 Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. SCK Input CMOS Note1 1 Serial clock input. Clock source used for reading from and writing to the control registers. VDD 18 Supply voltage for the RDRAM core and interface logic. VDDa 1 Supply voltage for the RDRAM analog circuitry. VCMOS 2 Supply voltage for CMOS input/output pins. GND 22 Ground reference for RDRAM core and interface. GNDa 2 Ground reference for RDRAM analog circuitry. DQA8..DQA0 Input / Output RSL Note2 9 Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. CFM Input RSL Note2 1 Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. CFMN Input RSL Note2 1 Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. VREF 1 Logic threshold reference voltage for RSL signals. CTMN Input RSL Note2 1 Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. CTM Input RSL Note2 1 Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. ROW2..ROW0 Input RSL Note2 3 Row access control. Three pins containing control and address information for row accesses. COL4..COL0 Input RSL Note2 5 Column access control. Five pins containing control and address information for column accesses. DQB8..DQB0 Input / Output RSL Note2 9 Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. Total pin count per package 80 Notes 1. All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero. 2. All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero. |
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