TLK4250

QUAD 1.0 to 2.5 Gbps TRANSCEIVER

SWRS025 − APRIL 2004

11

POST OFFICE BOX 655303

reference clock input

The reference clock (GTx_CLK) is an external input clock that synchronizes the transmitter interface. The

reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal

serialization bit clock is frequency locked to the reference clock and clocks out the serial transmit data on both

its rising and falling edges, providing a serial data rate that is 20 times the reference clock.

operating frequency range

The transceiver may operate at a serial data rate between 1.0 Gbps to 2.5 Gbps. GTx_CLK must be within

±100 PPM of the desired parallel data rate clock. Each individual channel may operate at a different rate.

testability

The transceiver has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed

testing of the transmit/receive portions of the circuitry. The ENABLEx terminal allows for all circuitry to be

disabled so that a quiescent current test can be performed.

loop-back testing

The transceiver can provide a self-test function by enabling (LOOPENx) the internal loop-back path. Enabling

this terminal causes serial transmitted data to be routed internally to the receiver. The parallel data output can

be compared to the parallel input data for functional verification. (The external differential output is held in a

high-impedance state during the loop-back testing.)

power-on reset

On application of minimum valid power, the transceiver generates a power-on reset. During the power-on reset,

the RDx terminals are 3-stated and Rx_CLK is held low. The length of the power-on reset cycle depends on the

GTx_CLK frequency, but is less than 1 ms in duration.