TLK4250

QUAD 1.0 to 2.5 Gbps TRANSCEIVER

SWRS025 − APRIL 2004

10

POST OFFICE BOX 655303

synchronization mode

The deserializer must synchronize to the serializer in order to receive valid data. Synchronization can be

accomplished in one of two ways.

rapid synchronization

The serializer has the capability to send specific SYNC patterns consisting of 9 ones and 9 zeros, switching at

the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the serializer signal

within a deterministic time frame. The transmission of SYNC patterns is selected via the SYNC input on the

serializer. On receiving a valid SYNC pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.

When the deserializer detects edge transitions at the serial input, it attempts to lock to the embedded clock

information. The deserializer LOCKBx output remains inactive while its clock/data recovery (CDR) locks to the

incoming data or SYNC patterns present on the serial input. When the deserializer locks to the serial data, the

LOCKBx output goes active. When LOCKBx is active, the deserializer outputs represent incoming serial data.

One approach is to tie the deserializer LOCKBx output directly to the SYNCx input of the transmitter. This

ensures that enough SYNC patterns are sent to achieve deserializer lock.

random lock synchronization

The deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns.

This allows the transceiver to operate in open-loop applications. Equally important is the deserializer’s ability

to support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data

stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact

lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation

between the incoming data and the GTx_CLK when the deserializer powers up.

The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer

could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive

multitransition (RMT). This occurs when more than one low-high transition takes place per clock cycle over

multiple clock cycles. In the worst case, the deserializer could become locked to the data pattern rather than

the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. On detection, the

circuitry prevents the LOCKBx from becoming active until the potential false-lock pattern changes. Notice that

the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does

not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does

not go into lock until it finds a unique data boundary that consists of four consecutive cycles of data boundary

(start/stop bits) at the same position.

The deserializer stays in lock until it cannot detect the same data boundary (start/stop bits) for four consecutive

cycles. Then the deserializer goes out of lock and hunts for the new data boundary (start/stop bits). In the event

of loss of synchronization, the LOCKBx terminal output goes inactive and the outputs (including Rx_CLK) enter

a high-impedance state. The user’s system must monitor the LOCKBx terminal in order to detect a loss of

synchronization. On detection of loss of lock, sending SYNC patterns for resynchronization is desirable if

reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as

previously noted. LOCKBx is held inactive for at least nine cycles after loss of lock is detected.

recommended power-up sequence

When powering up the device, it is recommended to first set the ENABLEx terminal low. Set the ENABLEx

terminal to high once sufficient time has passed to allow the power supply to stabilize.

power-down mode

When the ENABLEx terminal is deasserted low, the transceiver goes into a power-down mode. In the

power-down mode, the serial transmit terminals (DOUTTxP, DOUTTxN) and the receive data bus terminals

(RDx[0:17]) go into a high-impedance state.