Page 6

Version 1.41 Jan. 2004

K4R761869A

Packet Format

Figure 3 shows the formats of the ROWA and ROWR

packets on the ROW pins. Table 3 describes the fields which

comprise these packets. DR4T and DR4F bits are encoded to

contain both the DR4 device address bit and a framing bit

which allows the ROWA or ROWR packet to be recognized

by the RDRAM device.

The AV (ROWA/ROWR packet selection) bit distinguishes

between the two packet types. Both the ROWA and ROWR

packet provide a five bit device address and a five bit bank

address. An ROWA packet uses the remaining bits to specify

a nine bit row address, and the ROWR packet uses the

remaining bits for an eleven bit opcode field. Note the use of

the “RsvX” notation to reserve bits for future address field

extension.

Figure 3 also shows the formats of the COLC, COLM, and

COLX packets on the COL pins. Table 4 describes the fields

which comprise these packets.

The COLC packet uses the S (Start) bit for framing. A

COLM or COLX packet is aligned with this COLC packet,

and is also framed by the S bit.

The 23 bit COLC packet has a five bit device address, a five

bit bank address, a seven bit column address, and a four bit

opcode. The COLC packet specifies a read or write

command, as well as some power management commands.

The remaining 17 bits are interpreted as a COLM (M=1) or

COLX (M=0) packet. A COLM packet is used for a COLC

write command which needs bytemask control. The COLM

earlier. A COLX packet may be used to specify an indepen-

dent precharge command. It contains a five bit device

address, a five bit bank address, and a five bit opcode. The

COLX packet may also be used to specify some house-

keeping and power management commands. The COLX

packet is framed within a COLC packet but is not otherwise

associated with any other packet.

Table 3: Field Description for ROWA Packet and ROWR Packet

Field

Description

DR4T,DR4F

Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.

DR3..DR0

Device address for ROWA or ROWR packet.

BR4..BR0

Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the

AV

Selects between ROWA packet (AV=1) and ROWR packet (AV=0).

R9..R0

Row address for ROWA packet. RsvR denotes bits ignored by the

ROP10..ROP0

Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.

Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet

Field

Description

S

Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.

DC4..DC0

Device address for COLC packet.

BC4..BC0

Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0 ’ s).

C6..C0

Column address for COLC packet. RsvC denotes bits ignored by the

COP3..COP0

Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.

M

Selects between COLM packet (M=1) and COLX packet (M=0).

MA7..MA0

Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.

MB7..MB0

Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.

DX4..DX0

Device address for COLX packet.

BX4..BX0

Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’ s).

XOP4..XOP0