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TMS320C6722RFP250 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320C6722RFP250 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 115 page www.ti.com 2.5 Program Cache TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268C – MAY 2005 – REVISED NOVEMBER 2005 The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache has these key features: • Wide 256-bit path to internal ROM/RAM • Single-cycle access on cache hits • 2-cycle miss penalty to internal ROM/RAM • Caches external memory as well as ROM/RAM • Direct-mapped • Modes: Enable, Freeze, Bypass • Software invalidate to support code overlay The program cache line size is 256 bits wide and is matched with a 256-bit-wide path between cache and internal memory. This allows the program cache to fill an entire line (corresponding to eight C67x+ CPU instructions) with only a single miss penalty of 2 cycles. The program cache control registers are listed in Table 2-4. Table 2-4. Program Cache Control Registers REGISTER NAME BYTE ADDRESS DESCRIPTION L1PISAR 0x2000 0000 L1P Invalidate Start Address L1PICR 0x2000 0004 L1P Invalidate Control Register CAUTION Any application which modifies the contents of program RAM (for example, a program overlay) must invalidate the addresses from program cache to maintain coherency. The Cache Mode (Enable, Freeze, Bypass) is configured through a CPU internal register (CSR, bits 7:5). These options are listed in Table 2-5. Typically, only the Cache Enable Mode is used. But advanced users may utilize Freeze and Bypass modes to tune performance. Table 2-5. Cache Modes Set Through PCC Field of CSR CPU Register on C672x CPU CSR[7:5] CACHE MODE 000b Reserved - Not Supported 010b Enable - Cache is enabled, cache misses cause a line fill. 011b Freeze - Cache is enabled, but contents are unchanged by misses. 100b Bypass - Forces cache misses, cache contents frozen. Other Values Reserved - Not Supported CAUTION The C672x DSP reset value for CSR[7:5] is 000b, which it interprets as 010b. However, this applies only to C672x. For compatibility purposes, change CSR[7:5] to one of the supported modes listed in Table 2-5 during initialization. Device Overview 11 |
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