1

PS8626D

05/11/05

Vee

CLK_EN

CK_SEL

CLK0

Vee

CLK1

Vcc

Vcc

Q0

nQ0

nc

Q1

nQ1

Vcc

1

2

3

4

5

6

7

14

13

12

11

10

9

8

Vee

CLK_EN

CK_SEL

CLK0

nc/Vee

CLK1

nc/Vee

nc/Vee

nc/Vcc

Vcc

Q0

nQ0

Vcc

Q1

nQ1

Q2

nQ2

Vcc

Q3

nQ3

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Pin Configuration PI6C41204/A

Description

PI6C4120x is a high-performance LVCMOS or LVTTL to LVPECL

clock buffer. The PI6C41204 is a 4 output version with 2 select-

able inputs, pin compatible with ICS8535-01. PI6C41204A is the

enhanced version with extra power and ground pins to minimize

noise and jitter. The PI6C41202 is similar to the PI6C41204 except

it has two outputs.

20-Pin

Features

• Up to Four LVPECL outputs

• Selectable CLK0 or CLK1 inputs

• LVCMOSorLVTTLinputlevel

• 30ps max output skew

• 150ps max part-to-part skew

• 1.9ns max propagation delay

• 266 MHz output frequency

• Packaging(Pb-free&Greenavailable):

-14-pin TSSOP

- 20-pin TSSOP

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PI6C41202

PI6C41204

PI6C41204A

LVCMOS to LVPECL Driver

14-Pin

D

LE

CLK_SEL

CLK1

CLK0

CLK_EN

Q0

nQ0

Q

Q1

nQ1

Q2

nQ2

Q3

nQ3

0

1

D

LE

CLK_SEL

CLK1

CLK0

CLK_EN

Q0

nQ0

Q

Q1

nQ1

0

1

Block Diagram PI6C41202

Block Diagram PI6C41204/A

Pin Configuration PI6C41202