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TIMING CHARACTERISTICS

N

N+1

N+2

N+3

N+4

N

N−1

N−2

N−3

N + 1

N

N + 2

N + 3

N + 4

CLK, CLK

D[12:0],

OVR, OVR

DRY, DRY

AIN

T0073-01

TIMING CHARACTERISTICS

ADS5440

SLAS467 – JULY 2005

Figure 1. Timing Diagram

over full temperature range, 50% clock duty cycle, sampling rate = 210 MSPS, AV

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperature delay

ps

Clock slope independent aperature uncertainty (jitter)

fs

Clock slope jitter factor dependency

s/V

Latency

4

cycles

Clock Input

Clock period

4.76

ns

Clock pulsewidth high

2.38

ns

Clock pulsewidth low

2.38

ns

Clock to DataReady (DRY)

Clock rising to DataReady falling

3.06

ns

Clock rising to DataReady rising

5.44

ns

ns

ns

Data valid to clock (setup time)

0.64

ns

Clock to invalid Data (hold time)

4.39

ns

Data valid to DRY

2.42

ns

(1)

(2)

Data is updated with clock rising edge or DRY falling edge.

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