ZL30109

Data Sheet

2

Zarlink Semiconductor Inc.

Description

The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing

and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44 MHz output makes the

ZL30109 also suitable for SDH line card applications.

The ZL30109 generates a 19.44 MHz clock and ST-BUS and TDM bus clocks and framing signals that are

phase locked to one of two input references. It helps ensure system reliability by monitoring its references for

accuracy and stability and by maintaining stable output clocks during reference switching operations and during

short periods when a reference is unavailable.

The ZL30109 is intended to be the central timing and synchronization resource for network equipment that

complies with Telcordia, ETSI, ITU-T and ANSI network specifications.