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WM8591 Datasheet(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8591 Datasheet(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 50 page  Product Preview WM8591 w PP Rev 1.0 May 2005 9 MASTER CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 Master Clock Timing Requirements Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information ADC/DACMCLK System clock pulse width high tMCLKH 11 ns ADC/DACMCLK System clock pulse width low tMCLKL 11 ns ADC/DACMCLK System clock cycle time tMCLKY 27 ns ADC/DACMCLK Duty cycle 40:60 60:40 Table 1 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE – MASTER MODE Figure 2 Audio Interface – Master Mode ADCBCLK DOUT ADCLRC DIN DACLRC WM8591 CODEC DVD Controller DACBCLK |
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