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PI6CVF857 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6CVF857 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
1 / 14 page 1 PS8683B 10/17/03 ProductDescription PI6CVF857PLLclockdeviceisdevelopedforregisteredDDRDIMM applications. The device is a zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clockoutputs(Y[0:9],Y[0:9]),andonedifferentialpairfeedbackclock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V LVCMOS input (PWRDWN), and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receiversaredisabled,thePLListurnedoff,andthedifferentialclock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection fre- quency that is below the operating frequency of the PLL, the device willenteralowpowermode.Aninputfrequencydetectioncircuitwill detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CVF857 clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor- mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]). The PI6CVF857 is also able to track Spread Spectrum Clocking for reduced EMI. ProductFeatures • Operating Frequency up to 220 MHz for PC3200 Registered DIMM applications • Distributes one differential clock input pair to ten differential clock output pairs • Inputs(CLK,CLK)and(FBIN,FBIN) • Input PWRDWN: LVCMOS • Outputs (Yx,Yx),(FBOUT,FBOUT) • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input • Operatesat2.5VforPC1600,PC2100,PC2700, and2.6VforPC3200 • Packaging (Pb-free & Green available, select packages): – 48-pin TSSOP – 40-pin TQFN –56-ballVFBGA Block Diagram PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Y0 Y0 Y1 PWRDWN AVDD FBIN FBIN CLK CLK PLL Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT Powerdown and Test Logic |
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