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H8250 Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part No. H8250
Description  Universal Asynchronous Receiver/Transmitter
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Maker  ETC [List of Unclassifed Manufacturers]
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CAST H8250 Megafunction Datasheet
CAST, Inc.
Page 2
Pin Description
Name
Type
Polarity
Description
MR
In
High
Master Reset (Asynchronous)
CLK
In
-
Master clock (Should be Global Signal)
RCLK
In
-
Receiver clock (Recommended as Global Signal)
RD
In
High
Read control
WR
In
Falling
Write control (Recommended as Global Signal)
CS
In
High
Chip Select
DIN[7:0]
In
-
Data Input Bus
CTSn
In
Low
Clear-to -Send
DSRn
In
Low
Data Set Ready
DCDn
In
Low
Data Carrier Detect
SIN
In
-
Serial Input Data
RIn
In
Low
Ring Indicator
A[2:0]
In
-
Register Select
DOUT[7:0]
Out
-
Data Output Bus
SOUT
Out
-
Serial Output Data
DDIS
Out
High
Driver Disable
RTSn
Out
Low
Request-to-Send
DTRn
Out
Low
Data Terminal Ready
OUT1n
Out
Low
Output 1
OUT2n
Out
Low
Output 2
INTR
Out
High
Interrupt pending
BAUDOUTn
Out
Low
Baud Out
RXRDY
Out
Low
Receiver Ready to Receive Transmissions
TXRDY
Out
Low
Transmitter Ready to Transmit Data
Register Description
A(2:0)
Divisor *
Latch
Access Bit
Name
Symbol
Default
(reset)
value
No.
bits
Read/
Write
0
0
Receiver Buffer Register
RBR
XX
8
R
0
0
Transmitter Holding Register
THR
XX
8
W
0
1
Divisor Latch (LSB)
DLR
01h
8
R/W
1
1
Divisor Latch (MSB)
DMR
00h
8
R/W
1
0
Interrupt Enable Register
IER
00h
8
R/W
2
X
Interrupt Identification Register
IIR
01h
8
R
3
X
Line Control Register
LCR
00h
8
R/W
4
X
Modem Control Register
MCR
00h
8
R/W
5
X
Line Status Register
LSR
60h
8
R
6
X
Modem Status Register
MSR
00h
8
R
7
X
Scratch Register
SR
00h
8
R/W
*DLAB is the MSB of the Line Control Register
Switching Characteristics
Register Write
The Address (A) and Chip Select (CS) signals are not latched and therefore must be valid throughout the write
process. Writing is done at the falling edge of the WR signal.




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