Preliminary

18Mb 1x2Lp, HSTL, rev 1.1

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November 8, 2002

CXK79M36C162GB

The four AC timing parameters listed below are tested according to specific combinations of Output Clocks (CQs) and Out-

put Data (DQs):

Output Clock High to Output Data Valid (max)

Output Clock Low to Output Data Valid (max)

Output Clock High to Output Data Hold (min)

Output Clock Low to Output Data Hold (min)

The specific CQ / DQ combinations are defined as follows:

512Kb x 36

CQs

DQs

1K,2K

2E, 1F,2F, 1G,2G, 1H,2H, 1J,2J,

1R, 1T, 2T, 1U, 2U, 1V, 2V, 1W, 2W

10K, 11K 10A, 11A, 10B, 11B, 10C, 11C, 10D, 11D, 11E,

10L, 11L,10M,11M,10N,11N,10P,11P,10R