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CDCM7005ZVA Datasheet(PDF) 1 Page - Texas Instruments |
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CDCM7005ZVA Datasheet(HTML) 1 Page - Texas Instruments |
1 / 40 page www.ti.com FEATURES PIN ASSIGNMENTS (TOP VIEW) P0022-01 CP_OUT REF_SEL PRI_REF GND GND GND GND GND GND GND SEC_REF GND AVCC AVCC AVCC AVCC AVCC STATUS_ REF or PRI_SEC_ CLK GND GND GND GND GND VCC STATUS_ VCXO VCXO_IN GND VCC VCC VCC VCC VCC VCC Y0A GND GND GND GND GND VCC Y4B Y0B VCC VCC VCC VCC VCC VCC Y4A PD Y1A Y1B Y2A Y2B Y3A Y3B RESET or HOLD 1 2 3 4 5 6 7 8 A B C D F G H I_REF_CP or PLL_LOCK VBB VCC_CP CTRL_LE CTRL_CLK CTRL_ DATA VCXO_IN E P0023-01 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 45 44 43 42 46 47 48 24 23 22 21 20 16 17 18 19 15 14 13 Thermal Pad must be soldered to GND STATUS_REF or PRI_SEC_CLK STATUS_VCXO or I_REF_CP RESET HOLD or GND VCC VCC VCC VCC Y4B Y4A VCC VCC SEC_REF AVCC AVCC VBB VCC VCXO_IN VCC VCC Y0A Y0B VCC VCXO_IN CDCM7005 SCAS793A – JUNE 2005 – REVISED JUNE 2005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER or 48-Pin QFN (RGZ) • High Performance LVPECL and LVCMOS PLL • Industrial Temperature Range –40 °C to 85°C Clock Synchronizer • Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection • Accepts LVCMOS Input Frequencies Up to 200 MHz • VCXO_IN Clock is Synchronized to One of the Two Reference Clocks • VCXO_IN Frequencies Up to 2.2 GHz (LVPECL) • Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs) • Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually • Efficient Jitter Cleaning From Low PLL Loop Bandwidth • Low Phase Noise PLL Core • Programmable Phase Offset (PRI_REF and SEC_REF to Outputs) • Wide Charge Pump Current Range From 200 µA to 3 mA • Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs • Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O • Analog and Digital PLL Lock Indication • Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN) • Frequency Hold-Over Mode Improves Fail-Safe Operation • Power-Up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V • SPI Controllable Device Setting • 3.3-V Power Supply • Packaged in 64-Pin BGA (0,8 mm Pitch – ZVA) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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