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A49LF004TX-33C Datasheet(PDF) 10 Page - AMIC Technology |
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A49LF004TX-33C Datasheet(HTML) 10 Page - AMIC Technology |
10 / 10 page A49LF004 PRELIMINARY (November, 2003, Version 0.0) 9 AMIC Technology, Corp. Table 4: FWH Register Memory Map General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on the A49LF004. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register for the boot device appears at FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. See Table 5 for the GPI_REG bits and function. Table 5: General Purpose Inputs Register Block Locking Registers A49LF004 provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 6. Unused register locations will read as 00H. Write-Lock. The Write-Lock Bit determines whether the contents of the Block can be modified (using the Program or Erase Command). When the Write-Lock Bit is set to ‘1’, the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write-Lock Bit is reset to ‘0’, the block is not write protected through the Locking Register and may be modified unless write protected through some other means. If Top Block Lock, TBL#, is Low, VIL, then the Top Block (Block 7) is write protected and cannot be modified. Similarly, if Write Protect, WP#, is Low, VIL, then the Main Blocks (Blocks 0 to 6) are write protected and cannot be modified. After power-up or reset the Write-Lock Bit is always set to ‘1’ (write protected). Read-Lock. The Read-Lock bit determines whether the contents of the Block can be read (from Read mode). When the Read-Lock Bit is set to ‘1’, the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. When the Read-Lock Bit is reset to ‘0’, read operations in the Block return the data programmed into the block as expected. After power-up or reset the Read-Lock Bit is always reset to ‘0’ (not read protected). Lock-Down. The Lock-Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock-Down Bit is set to ‘1’, further modification to the Write-Lock, Read-Lock and Lock-Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the Lock- Down Bit is reset to ‘0’, the Write-Lock, Read-Lock and Lock-Down Bits can be changed. Memory Address Mnemonic Register Name Default Type FFBF0002h T_BLOCK_LK Top Block Lock Register (Block 7) 01h R/W FFBE0002h T_MINUS01_LK Top Block [-1] Lock Register (Block 6) 01h R/W FFBD0002h T_MINUS02_LK Top Block [-2] Lock Register (Block 5) 01h R/W FFBC0002h T_MINUS03_LK Top Block [-3] Lock Register (Block 4) 01h R/W FFBB0002h T_MINUS04_LK Top Block [-4] Lock Register (Block 3) 01h R/W FFBA0002h T_MINUS05_LK Top Block [-5] Lock Register (Block 2) 01h R/W FFB90002h T_MINUS06_LK Top Block [-6] Lock Register (Block 1) 01h R/W FFB80002h T_MINUS07_LK Top Block [-7] Lock Register (Block 0) 01h R/W FFBC0100h FGPI_REG FWH General Purpose Input Register N/A R FFBC0000h MANUF_REG Manufacturer ID Register 37h R FFBC0001h DEV_REG Device ID Register 95h R FFBC0003h CONT_REG Continuation ID Register 7Fh R Pin Number Bit Bit Name Function 32-PLCC 32-TSOP 7:5 - Reserved - - 4 FGPI[4] GPI_REG Bit 4 30 6 3 FGPI[3] GPI_REG Bit 3 3 11 2 FGPI[2] GPI_REG Bit 2 4 12 1 FGPI[1] GPI_REG Bit 1 5 13 0 FGPI[0] GPI_REG Bit 0 6 14 |
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