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ZL30105 Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc |
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ZL30105 Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc |
2 / 50 page ZL30105 Data Sheet 2 Zarlink Semiconductor Inc. Description The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to a system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the master-clock and slave-clock outputs even in the presence of high network jitter. The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications. |
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