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UT1553BRTIGPX Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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UT1553BRTIGPX Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 52 page  RTI-4 The host microprocessor gains access to the RTI internal registers by controlling input pins CS, CTRL, ADDR IN (10:0), and RD/WR. During message processing the host microprocessor should limit access to RTI internal registers. 1.1.2 Transparent Memory Access Configured in the transparent memory mode the host microprocessor accesses shared memory through the RTI. Arbitration for access to the bus is performed as discussed in section 1.1.1 of this document. When granted access to memory, the RTI asserts memory control signals ADDR OUT(10:0), RCS, and RRD/RWR. For host-controlled memory accesses the RAM memory address from the host is propagated from the Address In bus ADDR IN (10:0) to theAddress Out busADDR OUT (10:0). Memory control signals RD/WR and CS are also propagated through the RTI as RRD/RWR and RCS. Input CTRL is negated during all transparent memory accesses to prevent the RTI from inadvertently performing an internal register access or software reset. While CS is asserted, the RTI’s bidirectional Data bus DATA I/O (15:0) is an input (i.e., not actively driving bus). The host microprocessor gains access to the RTI internal registers by controlling input pins CS, CTRL, ADDR IN (10:0), and RD/WR. During message processing the host microprocessor should limit access to RTI internal registers. The host should not assert CS while the RTI is performing a memory access. 1.2 Internal Register Description The RTI uses three internal registers to allow the host to control the RTI operation and monitor its status. The host uses the following inputs Control (CTRL), Chip Select (CS), Read/Write (RD/WR), and ADDR IN (0) to read the 16-bit System Register or write to the 8-bit Control Register. The Control Register toggles bits in the MIL-STD-1553B status word, enables biphase inputs, selects terminal active flag, and puts the part in self-test. The System Register supplies operational status of the UT1553B RTI to the host. The Last Command Register saves the command word for a Transmit Last Command mode code, along with operational status from the System Register. Shared Memory Host Computer RTI UT1553B DMA CONTROLLER Figure 2. Direct Memory Access Configuration DATA(15:0) ADDR(10:0) CONTROL CONTROL Control Register (Write Only) Figure 3. Transparent Memory Access Configuration Shared Memory Host Computer RTI UT1553B DMA CONTROLLER DATA(15:0) ADDR IN (10:0) CONTROL ADDR OUT (10:0) CONTROL DATA I/O (15:0) |
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