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VT86C100A Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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VT86C100A Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 32 page  VIA Technologies, Inc. Preliminary VT86C100A 25 PAR T/S Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and valid one clock after the address phase. For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. 118 GNT# I Bus grant asserts to indicate to the VT86C100A that access to the bus is granted. 119 REQ# O Bus request is asserted by the bus master indicate to the bus arbiter that it wants to use the bus. 23 PERR# I/O Parity error asserts when a data parity error is detected 120 PME# O Power management event interrupt 111 HDRST O When PCIRST# is asserted low, the VT86C100A chip performs an internal system hardware reset. Then HDRST is asserted high for external device reset signal like PHY device. Network Interface 91 MCOL I Collision detect when the external PHY device 90 MCRS I Carrier sense is asserted by the external PHY when the media is active 92-95 MTXD[3-0] O MII 4 parallel transmit data lines. This data be synchronized to assertion by the MTXC signal 96 MTXEN O Transmit enable signals that the transmit is active in the MII port to an external PHY device 99 MTXC I MII transmit clock supports the 25mhz or 2.5mhz transmit clock supplied by the external PMD device. This clock should always be active. 100 MERR I MII receive error asserts when a data decoding error is detected by external PHY device. 101 MRXC I MII receive clock supports the 25mhz or 2.5mhz clock. This clock is recovered by the PHY. 102 MRXDV I MII data valid 103-106 MRXD[0-3] I Four parallel receive data lines. This data be driven from external PHY be synchronized with MRXC signal. 109 MDC O MII management data clock be soured by VT86C100A MDC bit (MIIR:0) to the external PHY devices as timing reference for the MDIO signal. 110 MDIO I/O MII management data input/output, read from MDI bit (MIIR:1) or written from MDO bit (MIIR:2) 112 GPIO I/O GPIO External Memory Support & General purpose I/O support 49 EECS O EEPROM Chip Select: Chip select signal for the external EEPROM when a EEPROM is used to provide the configuration data and Ethernet Address. A 100K pull-up resistor is connected. 50 BPRD# O Boot PROM Read: Read the Boot ROM on the memory support data bus. 51 MD0/ EEDO I/O Bootrom data 0 Serial ROM Data output 52 MD1/ EEDI O/O Bootrom data 1 Serial ROM Data input 53 MD2/ EECLK O/O Bootrom data 2 Serial ROM Clock signal 54-55,58- 60 MD3-7 I/O Bootrom Data [3-7] : |
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Similar Description - VT86C100A |
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