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5962-01A1701Q9A Datasheet(PDF) 8 Page - ATMEL Corporation |
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5962-01A1701Q9A Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 31 page  8 TSS901E Rev. C – 24-Aug-01 Register Address Map The addresses of the TSS901E registers are directly mapped with pins HADR7 - 0. The tables below shows the addresses of all the TSS901E registers depending on the HOCI port width. TSS901E status and control registers TSS901E channel 1 status and control registers Port Width / Address (hex) Register Function Reset Value (hex) Access 32 16 8 00 00 00 SICR TSS901E Interface Control Register 00 r / w 01 01 01 TRS_CTRL Transmit-Speed-Base Register 0A r / w 02 02 02 ROUTE_CTRL Routing Enable / Status Register 00 r 03 03 03 reserved 00 04 04 06 04 05 06 07 ISR Interrupt Status Register 04010040 ro 08 08 0A 08 09 0A 0B IMR Interrupt Mask Register 00000000 r / w 0C 0C 0C COMI_CS0R COMI Chip Select 0 upper address boundary Register FF r / w 0D 0D 0D reserved 00 0E 0E 0E COMI_ACR COMI Arbitration Control Register 08 r / w 0F 0F 0F PRCIR PRCI Register 00 r / w Port Width / Address (hex) Register Function Reset Value (hex) Access 32 16 8 10 10 10 CH1_DSM_MODR channel 1 DSM mode Register 03 r / w 11 11 11 CH1_DSM_CMDR channel 1 DSM command Register 00 r / w 12 12 12 CH1_DSM_STAR channel 1 DSM status Register 00 r / w 13 13 13 CH1_DSM_TSTR channel 1 DSM test Register 00 r / w 14 14 14 CH1_ADDR channel 1 address Register 00 r / w 15 15 15 CH1_RT_ADDR channel 1 Route Address Register 00 r / w 16 16 16 CH1_PR_STAR channel 1 Protocol Status Register 04 r / w 17 17 17 reserved 00 --- |
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