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SCAN182245FSSCQB Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SCAN182245FSSCQB
Description  Non-Inverting Transceiver with 25OHM Series Resistor Outputs
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SCAN182245FSSCQB Datasheet(HTML) 11 Page - National Semiconductor (TI)

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SCAN ABT Live Insertion and Power Cycling Characteristics
SCAN ABT is intended to serve in Live Insertion backplane
applications It provides 2nd Level Isolation1 which indicates
that while external circuitry to control the output enable pin
is unnecessary there may be a need to implement differen-
tial length backplane connector pins for VCC and GND As
well pre-bias circuitry for backplane pins may be necessary
to avoid capacitive loading effects during live insertion
SCAN ABT provides control of output enable pins during
power cycling via the circuit in
Figure A It essentially con-
trols the Gn pin until VCC reaches a known level
During
power-up when VCC ramps through the 00V to 07V
range all internal device circuitry is inactive leaving output
and IO pins of the device in high impedance From approxi-
mately 08V to 18V VCC the Power-On-Reset circuitry
(POR) in
Figure A becomes active and maintains device
high impedance mode The POR does this by providing a
low from its output that resets the flip-flop The output Q of
the flip-flop then goes high and disables the NOR gate from
an incidental low input on the Gn pin After 18V VCC the
POR circuitry becomes inactive and ceases to control the
flip-flop To bring the device out of high impedance the Gn
input must receive an inactive-to-active transition a high-to-
low transition on Gn in this case to change the state of the
flip-flop With a low on the Q output of the flip-flop the NOR
gate is free to allow propagation of a Gn signal
During
power-down the Power-On-Reset circuitry will be-
come active and reset the flip-flop at approximately 18V
VCC Again the Q output of the flip-flop returns to a high and
disables the NOR gate from inputs from the Gn pin The
device will then remain in high impedance for the remaining
ramp down from 18V to 00V VCC
Some suggestions to help the designer with live insertion
issues
 The Gn pin can float during power-up until the Power-On-
Reset circuitry becomes inactive
 The Gn pin can float on power-down only after the Pow-
er-On-Reset has become active
The description of the functionality of the Power-On-Reset
circuitry can best be described in the diagram of
Figure B
TLF11657 – 19
FIGURE A
TLF11657 – 20
FIGURE B
1Section 7 ‘‘Design Consideration for Fault Tolerant Backplanes’’ Application Note AN-881
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices
http
www nationalcom
11


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