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MU9C8K64-12TDC Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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MU9C8K64-12TDC Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 30 page  Register Descriptions MU9C Binary Routing Coprocessor (RCP) Family Rev. 6 9 PA:AA Bus After a Random Access Read or Write to the CAM After a random Read or Write cycle to the MU9C, the PA:AA bus carries the address that was accessed during that cycle. Only the device in which the access occurred enables its PA:AA bus. All other devices keep their PA:AA bus in high-impedance regardless of the state of their /OE inputs. Note that the access to the PA:AA bus differs in this respect from the operation of the Status register, which is accessible in any selected device under this particular circumstance. In the event that the Write cycle was broadcast to multiple devices, all devices that have their /OE lines held LOW will enable their PA:AA bus. Under this circumstance, it is up to the system designer to ensure that only one /OE line is driven LOW to prevent bus contention on the PA:AA bus. PA:AA Bus Conditions of Operation • During a control state that does not have any effect on the device address, such as a Write Register cycle, the PA:AA bus remains unchanged. In other words, the state of the PA:AA bus persists until another cycle causes it to change. • When enabled by /OE being LOW, the PA:AA bus is only free to change while /E is HIGH. When /E goes LOW the PA:AA bus is latched. • The PA:AA bus is enabled when /OE is LOW provided that the previous cycle causes them to be active. When /OE is HIGH, the PA:AA bus is in high-impedance. Note that /OE is asynchronous with respect to /E, and is independent of Chip Select from either /CS1, /CS2, or through the Device Select register, except in the case of non-broadcast random Read and Write cycles to the MU9C. PA:AA Bus and the Match Flags The Match flags /MF and /MM reflect the results of the most recent Comparison cycle. During a Comparison cycle, they do not change until after /E has gone HIGH after which they are free to change combinatorially; their state is latched when /E is LOW. This condition allows some pipelining to occur and is useful in systems with long daisy chains. A Comparison cycle can be followed by another cycle that does not affect the PA:AA bus before the daisy chain is resolved. For example: The WRL CR control state can be executed before the daisy chain has resolved device prioritization after the CMP CR control state. The /OE then is asserted at a suitable time, depending on the length of the daisy chain. The Match address of the highest-priority responding device then is driven onto the PA:AA bus. The /MF, /MM lines continue to indicate the results of the most recent match, even when the PA:AA bus carries an address other than the Match address. This condition allows rapid return to the Match address value on the PA:AA bus lines through a RDL[HPM] cycle, without the daisy chain having to re-resolve device-level prioritization. PA:AA Bus and the Status Register The Status Register bits SR15–0 reflect the PA:AA bus under all conditions. The Status Register flags /MF, /MM, and /FF represent the local conditions within the device, and are not conditioned by the /MI and /FI inputs. After a Comparison cycle, Write at Next Free address, or access to the Highest-Priority Matching device, a Status Register Read cycle is executed in the same device as the active PA:AA bus. In the case of a random access Read or Write cycle, the Status register of any selected device can be accessed by a Read Status Register cycle. The system designer must ensure that a Status Register Read cycle after a random Read or Write cycle is into a single device using Chip Select /CS1, /CS2, or the Device Select register to prevent bus contention on the DQ31–0 bus. REGISTER DESCRIPTIONS The Comparand register, seven mask registers, Address register, Configuration register, Status register, Next Free Address register, Device Select register, and Instruction register comprise the register set. Note that all RESERVED bits can be read and written without affecting the operation of the device. However, for forward compatibility with future product enhancements, system designers should not rely on any particular RESERVED bit having no effect on the operation of the device in future revisions. Therefore all RESERVED bits should be set to logical zero. The Register Set Comparand Register The 64-bit Comparand register holds the value to be compared with the valid contents of the Address Database array, although the DQ lines can be compared directly, and then optionally written into the Comparand register. CMP CR WR CR |
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