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MU9C4K64-90TDI Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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MU9C4K64-90TDI Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 30 page  MU9C Binary Routing Coprocessor (RCP) Family Operational Characteristics 8 Rev. 6 HIGH) participate in the operation. The AC8–6 lines select the mask register and the AC5–0 lines provide the Op-Code. If masking is not used, and all random addressing of the memory is indirect through the Address register, then only the DSC and AC5–0 lines are needed for full control of the device. In applications where a restricted number of control lines are available, or where speed is not critical, the MU9C RCP can be controlled in Software Control mode where the control states are loaded into the Instruction register through the DQ31–0 lines. The control states are identical in both Hardware and Software Control modes, although DQ12 and DQ13 take on special significance in Software mode. Software Control For optimum performance, the AC bus and DSC line control the MU9C RCP, allowing data transactions through the DQ31–0 lines during a control cycle. In cases where the overhead of a separate data load cycle can be accommodated, the MU9C RCP can be operated through the Instruction register. The AC bus and DSC line are not used. Control through the Instruction register is selected by the FR27–26 bits of the Configuration register being set HIGH. The instruction is loaded from the DQ11–0 lines (with DSC on DQ12) into the Instruction register during a Write cycle with the /AV line HIGH. The instructions are directly analogous to the control states for any operation that does not involve data transfer on the DQ31–0 lines, in which case the instruction is executed during the same cycle as the instruction is loaded. To distinguish between Read and Write control states, DQ13 is used to indicate which type of instruction should be executed. When DQ13 is LOW at the beginning of the cycle, the instruction executed is the Write Cycle instruction (/W = LOW when control state is conveyed on AC bus and DSC); when DQ13 is HIGH at the beginning of the cycle, the instruction executed is the Read Cycle instruction (/W = HIGH when control state is conveyed on the AC bus). When the instruction calls for data to be written or read from the DQ31–0 lines, the instruction is loaded into the Instruction register during the cycle, and the next Data Read or Write cycle with /AV LOW executes the instruction using the DQ31–0 bus for the data transaction. The instruction is persistent; for example, if no other instruction is loaded into the Instruction Register, subsequent data transactions with the /AV line LOW will be executed according to the instruction currently loaded in the Instruction register. When there is a data access to a memory location on DQ31–0 associated with the instruction, the /VB line carries the validity of that location. Instructions that involve data transactions on DQ31–0, and are therefore executed on a subsequent Read or Write cycle with the /AV line LOW, are all Read/Write Memory and Read/Write Register instructions, Read Validity, Write PA3-0. All other instructions are executed in a single cycle with the state of DQ13 being interpreted as the state of the /W line during the equivalent hardware control state. For Read Cycles with the /AV line HIGH, there is a Software Control mode. This mode is selected through the Configuration bits FR27–26. In Software Control mode (FR27–26 = 0b11) a Read cycle with /AV HIGH accesses the Status register. Active Address Interface PA:AA Bus The Active Address interface PA:AA bus carries the currently active address. The address source depends on the most recent control state that caused it to change. The possible address sources that are output on PA:AA bus are: Highest-Priority Match address, Next Free address, Read address, and Write address. PA:AA Bus After a Comparison Cycle After a Comparison cycle, or access to the Highest-Priority address, the PA:AA bus carries one of the following two possible results: • The Match address if the Comparison cycle resulted in a match in the MU9C. Only the device containing the highest-priority match enables its PA:AA bus. All other devices with either no match or a lower-priority match, as indicated by the Match Flag daisy chain, keep their PA:AA bus in high-impedance regardless of the state of their /OE inputs. • All 1s if there was no match in the MU9C. The lowest-priority device, as indicated by bit FR25 in the Configuration register, enables its PA:AA bus and provides the source of all 1s. All other devices will keep their PA:AA bus in high-impedance regardless of the state of their /OE inputs. PA:AA Bus After a Write at Next Free Address Cycle After a Write at Next Free Address cycle the PA:AA carries the address that was written to during that cycle. Only the device in which the write occurred enables its PA:AA bus. All other devices keep their PA:AA bus in high-impedance regardless of the state of their /OE inputs. In the event that the system was full prior to the Write at Next Free Address cycle being executed, so that the write operation was suppressed, the PA:AA carries all 1s. The lowest-priority device, as indicated by bit FR25 in the Configuration register, enables its PA:AA bus and provides the source of all 1s. All other devices keep their PA:AA in high-impedance regardless of the state of their /OE inputs. |
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