Rev. 1.3 Aug. 2005

256MB, 512MB Unbuffered DIMMs

DDR2 SDRAM

DDR2 Unbuffered DIMM Ordering Information

Note: “Z” of Part number(11th digit) stand for Lead-free products.

Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.

Part Number

Density

Organization

Component Composition

Number of Rank

Height

x64 Non ECC

M378T3253FG(Z)3-CE6/D5/CC

256MB

32Mx64

32Mx8(K4T56083QF)*8

1

30mm

M378T3253FG(Z)0-CE6/D5/CC

256MB

32Mx64

32Mx8(K4T56083QF)*8

1

30mm

M378T6453FG(Z)3-CE6/D5/CC

512MB

64Mx64

32Mx8(K4T56083QF)*16

2

30mm

M378T6453FG(Z)0-CE6/D5/CC

512MB

64Mx64

32Mx8(K4T56083QF)*16

2

30mm

x72 ECC

M391T3253FG(Z)3-CE6/D5/CC

256MB

32Mx72

32Mx8(K4T56083QF)*9

1

30mm

M391T3253FG(Z)0-CE6/D5/CC

256MB

32Mx72

32Mx8(K4T56083QF)*9

1

30mm

M391T6453FG(Z)3-CE6/D5/CC

512MB

64Mx72

32Mx8(K4T56083QF)*18

2

30mm

M391T6453FG(Z)0-CE6/D5/CC

512MB

64Mx72

32Mx8(K4T56083QF)*18

2

30mm

Features

• Performance range

• JEDEC standard 1.8V ± 0.1V Power Supply

• 4 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Package: 60ball FBGA - 32Mx8

• All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

E6(DDR2-667)

D5(DDR2-533)

CC(DDR2-400)

Unit

Speed@CL3

400

400

400

Mbps

Speed@CL4

533

533

400

Mbps

Speed@CL5

667

-

-Mbps

CL-tRCD-tRP

5-5-5

4-4-4

3-3-3

CK

Address Configuration

Organization

Row Address

Column Address

Bank Address

Auto Precharge

32Mx8(256Mb) based Module

A0-A12

A0-A9

BA0-BA1

A10