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M366S3323CT0-C1L Datasheet(PDF) 2 Page - Samsung semiconductor |
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M366S3323CT0-C1L Datasheet(HTML) 2 Page - Samsung semiconductor |
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2 / 7 page  SERIAL PRESENCE DETECT PC100 Unbuffered DIMM Rev 0.1 Apr. 2000 M366S1724CT0-C1H/C1L Byte # Function Described Function Supported Hex value Note -1H -1L -1H -1L 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 Total # of bytes of SPD memory device 256bytes (2K-bit) 08h 2 Fundamental memory type SDRAM 04h 3 # of row address on this assembly 12 0Ch 1 4 # of column address on this assembly 9 09h 1 5 # of module Rows on this assembly 2 Rows 02h 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time @CAS latency of 3 10ns 10ns A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 60h 60h 2 11 DIMM configuration type Non parity 00h 12 Refresh rate & type 15.625us, support self refresh 80h 13 Primary SDRAM width x16 10h 14 Error checking SDRAM width None 00h 15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h 16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh 17 SDRAM device attributes : # of banks on SDRAM device 4 banks 04h 18 SDRAM device attributes : CAS latency 2 & 3 06h 19 SDRAM device attributes : CS latency 0 CLK 01h 20 SDRAM device attributes : Write latency 0 CLK 01h 21 SDRAM module attributes Non-buffered, non-registered & redundant addressing 00h 22 SDRAM device attributes : General +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 0Eh 23 SDRAM cycle time @CAS latency of 2 10ns 12ns A0h C0h 2 24 SDRAM access time from clock @CAS latency of 2 6ns 7ns 60h 70h 2 25 SDRAM cycle time @CAS latency of 1 - - 00h 00h 26 SDRAM access time from clock @CAS latency of 1 - - 00h 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 14h 14h 28 Minimum row active to row active delay (tRRD) 20ns 20ns 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 14h 14h 30 Minimum activate precharge time (=tRAS) 50ns 50ns 32h 32h 31 Module Row density 2 Rows of 64MB 10h 32 Command and address signal input setup time 2ns 2ns 20h 20h 33 Command and address signal input hold time 1ns 1ns 10h 10h 34 Data signal input setup time 2ns 2ns 20h 20h • Organization : 16Mx64 • Composition : 8Mx16 *8 • Used component part # : K4S281632C-TC1H/C1L • # of rows in module : 2 Rows • # of banks in component : 4 banks • Feature : 1,375mil height & double sided component • Refresh : 4K/64ms • Contents ; |
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