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LTC4556EUF Datasheet(PDF) 7 Page - Linear Technology |
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LTC4556EUF Datasheet(HTML) 7 Page - Linear Technology |
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7 / 20 page  LTC4556 7 4556f SCLK. DOUT can be connected directly to a microcontroller or the DIN pin of another LTC4556 or LTC1955 for daisy chained operation. SCLK (Pin 23): Input. The SCLK pin clocks the serial port. Each new data bit is received on the rising edge of SCLK. SCLK should be left high during idle times and should not be clocked when LD is low. LD (Pin 24): Input. The falling edge of this pin loads the current state of the shift register into the command regis- ter. Command changes to the smart card will be updated on the falling edge of LD. The rising edge of LD latches status information into the shift register for the next read/ write cycle. SGND (Pin 25): Exposed Pad. Must be soldered to PCB Ground. UNDERV (Pin 20): Input. The UNDERV pin provides security by supplying a precision undervoltage threshold for external supply monitoring. An external resistive volt- age divider programs the desired undervoltage threshold. Once UNDERV falls below 1.23V, the LTC4556 automati- cally begins the deactivation sequence. If external supply monitoring is not required, the UNDERV pin should be connected to either VBATT or DVCC. DIN (Pin 21): Input. Input for the serial port. Command data is shifted into DIN synchronously with SCLK. DIN can be connected directly to a microcontroller or the DOUT pin of another LTC4556 or LTC1955 for daisy chained operation. DOUT (Pin 22): Output. Output for the serial port. Smart card status data is shifted out of DOUT synchronously with PI FU CTIO S BLOCK DIAGRA C4 C8 I/O RST CLK VCC VBATT DVCC GND CHARGE PUMP FAULT UNDERV 1.23V PRES 4556 BD SMART CARD SOCKET DIGITAL SUPPLY SMART CARD COMMUNICATIONS SERIAL PORT COMMAND/STATUS DATA C+ C– CPO + – RESET CONTROL LOGIC STATUS DATA COMMAND LATCH SHIFT REGISTER + – τ DIN DOUT SCLK LD CLOCK CONTROL LOGIC CHARGE PUMP DATA ASYNC SYNC RIN 24 23 22 21 3 4 5 2 6 1 20 19 15 14 18 17 13 11 9 8 10 12 LDO 16 |
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