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K4D551638D-TC50 Datasheet(PDF) 8 Page - Samsung semiconductor |
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K4D551638D-TC50 Datasheet(HTML) 8 Page - Samsung semiconductor |
8 / 18 page 256M GDDR SDRAM K4D551638D-TC - 8 - Rev 1.8 (Oct. 2003) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. MODE REGISTER SET(MRS) Mode Register CAS Latency A6 A5 A4 Latency 000 Reserved 001 Reserved 010 Reserved 011 3 100 4 101 Reserved 110 Reserved 111 Reserved Burst Length A2 A1 A0 Burst Type Sequential Interleave 0 0 0 Reserve Reserve 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve Burst Type A3 Type 0 Sequential 1 Interleave * RFU(Reserved for future use) should stay "0" during MRS cycle. MRS Cycle Command *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. 0 CK, CK Precharge NOP NOP MRS NOP NOP 2 01 5 34 8 67 Any NOP All Banks Command tRP tMRD=2 tCK BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 An ~ A0 0MRS 1EMRS DLL A8 DLL Reset 0No 1Yes Test Mode A7 mode 0 Normal 1Test NOP Address Bus RFU 0 RFU DLL TM CAS Latency BT Burst Length |
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