- 10 -

Rev 1.0

July 2002

K7Q163652A

K7Q161852A

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.

3. If C,C are tied high, K,K become the references for C,C timing parameters.

(0

°C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 2.4V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

PARAMETER

SYMBOL

-16

-13

-10

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time(K, K, C, C)

6

7.5

10

ns

Clock HIGH time (K, K, C, C)

2.4

3.0

3.5

ns

Clock Low time (K, K, C, C)

2.4

3.0

3.5

ns

Clock to clock (K

↑ → K↑, C↑ → C↑)

2.7

3.3

3.4

4.1

4.6

5.4

ns

Clock to data clock (K

↑ → C↑, K↑→ C↑)

0.0

2.0

0.0

2.5

0.0

3.0

ns

Output Times

C, C High to Output Valid

2.5

3.0

3.0

ns

3

C, C High to Output Hold

1.2

1.2

1.2

ns

3

C High to Output High-Z

2.5

3.0

3.0

ns

3

C High to Output Low-Z

1.2

1.2

1.2

ns

3

Setup Times

Address valid to K rising edge

0.7

0.8

1.0

ns

Control inputs valid to K rising edge

0.7

0.8

1.0

ns

2

Data-in valid to K, K rising edge

0.7

0.8

1.0

ns

Hold Times

K rising edge to address hold

0.7

0.8

1.0

v

K rising edge to control inputs hold

0.7

0.8

1.0

ns

K, K rising edge to data-in hold

0.7

0.8

1.0

ns

PARAMETER

SYMBOL

MIN

MAX

UNIT

Supply Voltage

2.4

2.6

V

1.4

1.9

V

Reference Voltage

0.68

0.95

V

Ground

0

0

V

Undershoot Timing

Overershoot Timing