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IDT82V1068PF Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT82V1068PF Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 56 page 9 IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE DX2 O 49 Transmit PCM Data Output 2 (for MPI Mode) This pin remains in high-impedance state until a pulse appears on the FS pin. The PCM data is output through the DX1 or DX2 pin as selected by Local Command 7, following the bit clock signal on the BCLK pin. This pin is not used in GCI mode. DR1/DD I 45 DR1: Receive PCM Data Input 1 (for MPI Mode) In MPI mode, the PCM data is received from the DR1 or DR2 pin as selected by Local Command 8, following the bit clock signal on the BCLK. DD: GCI Data Downstream (for GCI Mode) In GCI mode, the data downstream of all eight channels is received serially on the DD pin. The time slot assignment for the eight channels is determined by the CCLK/TS pin. DR2 I 48 Receive PCM Data Input 2 (for MPI Mode). In MPI mode, the PCM data is received from the DR1 or DR2 pin as selected by Local Command 8, following the bit clock signal on the BCLK pin. This pin is not used in GCI mode. FS/FSC I 52 FS: Frame Synchronization signal (for MPI Mode) In MPI mode, the FS signal is an 8 kHz synchronization signal that identifies the beginning of the PCM frame. FSC: Frame Sync signal (for GCI Mode) In GCI mode, the FSC signal is an 8 kHz synchronization signal that identifies the beginning of the GCI frame. BCLK/DCL I 53 BCLK: Bit Clock (for MPI Mode) In MPI mode, the PCM data is transmitted through the DX1 or DX2 pin and received from the DR1 or DR2 pin following the signal on the BCLK pin. The frequency of the BCLK may vary from 512 kHz to 8.192 MHz. The BCLK signal is required to be synchronous to the FS signal. DCL: Data Clock (for GCI Mode) In GCI mode, the DCL signal is either 2.048 MHz or 4.096 MHz, selected by the CI/DOUBLE pin. If the CI/DOUBLE pin is logic low, the DCL signal is 2.048 MHz; If the CI/DOUBLE pin is logic high, the DCL signal is 4.096 MHz. It is recommended to connect the MCLK and DCL pins together. TSX1 O47 Transmit Output Indicator 1 (for MPI Mode) This is an open drain output. It becomes low when the PCM data is transmitted through the DX1 pin. This pin is not used in GCI mode. TSX2 O50 Timeslot Indicator Output 2 (for MPI Mode) This is an open drain output. It becomes low when the PCM data is transmitted through the DX2 pin. This pin is not used in GCI mode. CS I109 Chip Selection (for MPI Mode). In MPI mode, a logic low on this pin enables the Serial Control Interface. CI/DOUBLE I 111 CI: Serial Control Interface Data Input (for MPI Mode) In MPI mode, the control data from the master processor is input to the CODEC through the CI pin. The data rate is determined by the CCLK signal. DOUBLE: Double/Single DCL Selection (for GCI Mode) In GCI mode, the DOUBLE pin is used to determine the frequency of the DCL signal. When low, the DCL frequency is 2.048 MHz; when high, the DCL frequency is 4.096 MHz. CO O 112 Serial Control Interface Data Output (tri-state) (for MPI Mode) In MPI mode, the serial control interface data is output from the CODEC to the master processor through the CO pin. The data rate is determined by the CCLK signal. This pin is in high impedance state when the CS pin is logic high. The CO pin is not used in GCI mode. CCLK/TS I 110 CCLK: Serial Control Interface Clock (for MPI Mode) In MPI mode, this is the clock for the Serial Control Interface. It can be up to 8.192 MHz. TS: Timeslot Selection (for GCI Mode) In Compressed GCI mode, the TS pin indicates which half of the 8 continuous GCI timeslots is used. When the TS pin is low, timeslots 0-3 are selected; when this pin is high, timeslots 4-7 are selected. In Linear GCI mode, the TS pin indicates which half of the 8 continuous GCI timeslots is used for voice signals. When this pin is low, timeslots 0-3 are used for linear voice data, timeslots 4-7 are used for Monitor channel and C/I octet. When this pin is high, timeslots 4-7 are used for linear voice data, timeslots 0-3 are used for Monitor channel and C/I octet. Name Type Pin Number Description |
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