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HD40A4368F Datasheet(PDF) 11 Page - Hitachi Semiconductor

Part # HD40A4368F
Description  4-bit HMCS400-Series microcomputer
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Manufacturer  HITACHI [Hitachi Semiconductor]
Direct Link  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HD40A4368F Datasheet(HTML) 11 Page - Hitachi Semiconductor

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HD404369 Series
11
Bit 3
Bit 2
Bit 1
Bit 0
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of
INT1)
IF1
(IF of
INT1)
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
IMS
(IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
$000
$001
$002
$003
Interrupt control bits area
IM0
(IM of
INT0)
IF0
(IF of
INT0)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
ICSF
(Input capture
status flag)
$020
$021
$022
$023
Register flag area
DTON
(Direct transfer
on flag)
ADSF
(A/D start flag)
WDON
(Watchdog
on flag)
LSON
(Low speed
on flag)
ICEF
(Input capture
error flag)
RAME
(RAM enable
flag)
IAOF
(IAD off flag)
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Bit 3
Bit 2
Bit 1
Bit 0
Not used
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
LSON
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
DTON
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Inhibited
Allowed
Not executed
Inhibited
Allowed
Inhibited
Allowed
Not executed in active mode
Allowed
Allowed
Used in subactive mode
Not executed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by
STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions


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