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87973DYI-147 www.icst.com/products/hiperclocks.html REV. A AUGUST 26, 2003 1 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PIN ASSIGNMENT GENERAL DESCRIPTION The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™fam- ily of High Performance Clock Solutions from ICS. The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The ICS87973I-147 is a highly flexible device. The three select- able inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output fre- quency range is 10MHz to 150MHz.The input frequency range is 6MHz to 120MHz. The ICS87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur.This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer mul- tiples of one another. Example Applications: 1. System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. FEATURES • Fully integrated PLL • 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 10MHz to 150MHz • VCO range: 240MHz to 500MHz • Output skew: 200ps (maximum) • Cycle-to-cycle jitter, (all banks ÷ 4): 55ps (maximum) • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Pin compatible with MPC973 • Compatible with PowerPC™andPentium™ Microprocessors HiPerClockS™ ICS 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View ICS87973I-147 |
