Rev 0.7 / Oct. 2004

7

HY27SS(08/16)561M Series

HY27US(08/16)561M Series

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash

MEMORY ARRAY ORGANIZATION

The memory array is made up of NAND structures where 16 cells are connected in series.

The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the

main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used

to store Error correction Codes, software flags or Bad Block identification.

In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes.

In the x16 devices the pages are split into a 256 Word main area and an 8 Word spare area. Refer to Figure 8, Memory

Array Organization.

Bad Blocks

The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks that contain one or more

invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device.

The Bad Block Information is written prior to shipping (refer to Bad Block Management section for more details).

The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that

could develop later on.

These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes.

Figure 7. Memory Array Organization

1st half Page

(256 bytes)

2nd half Page

(256 bytes)

Block

Page

512 Bytes

16

Bytes

8 bits

8 bits

512 Bytes

16

Bytes

Page Buffer, 528 Bytes

x8 DEVICES

Block= 32 Pages

Page= 528 Bytes (512+16)

Main Area

Block

Page

256 Words

8

Words

16 bits

16 bits

256 Words

8

Words

Page Buffer, 264 Words

x16 DEVICES

Block= 32 Pages

Page= 264 Bytes (256+8)

Sp

are

Ar

ea