THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

11

POST OFFICE BOX 655303

0

1023

0

700

512

400

50

800

64

960

300 mV

800 mV

700 mV

300 mV

Illegal Color

Difference Outputs

Input

Codes

VO

mV

0

Figure 4. CbCr Outputs, Reduced-Scale Input Code Range

output amplitude control

connected between FSADJ and AVSS. In all operation modes the relative amplitudes of these current drivers

The sync generator is composed of different current sources that are internally routed to a corresponding DAC

output. Since they are additional to the video DACs, full 10-bit DAC resolution is preserved for video. Depending

on the setting of INS3_INT during SYNC low, the sync current drive is added to either only the green channel

output (sync-on-G/Y) if INS3_INT=L or all three channel outputs (sync-on-all) if INS3_INT=H. Sync insertion

is only available in video DAC mode.

input. When using reduced-scale range, the codes on the G/Y channel are not internally scaled (only BCb and

by a factor of 1023/(940-64) to map the reduced-scale Y input code range to the same output current drive level.

Since these are the current drive levels for the video DACs they do not take into account the additional dc bias

for sync insertion when using video DAC mode. The voltage compliance outputs in Figure 5 assume termination

with a 37.5-

Ω resistor.