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MAX1144ACAP Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX1144ACAP Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 18 page 14-Bit ADCs, 150ksps, 3.3V Single Supply 4 _______________________________________________________________________________________ PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Hysteresis VHYST 0.2 V Input Capacitance CIN 10 pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 0.5mA DVDD - 0.5 V ISINK = 5mA 0.4 Output Low Voltage VOL ISINK = 16mA 0.8 V Three-State Leakage Current IL CS = DVDD -10 +10 µA Three-State Output Capacitance CS = DVDD 10 pF POWER SUPPLIES Analog Supply AVDD 3.135 3.3 3.465 V Digital Supply DVDD 3.135 3.3 3.465 V Unipolar mode 3.9 8 Bipolar mode 7 11 mA Analog Supply Current IANALOG SHDN = 0, or software power-down mode 0.1 10 µA Unipolar or bipolar mode 1 2 mA Digital Supply Current IDIGITAL SHDN = 0, or software power-down mode 1.1 10 µA Power-Supply Rejection Ratio (Note 8) PSRR AVDD = DVDD = 3.135V to 3.465V 65 dB ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF = 2.048V, CREF = 4.7µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) TIMING CHARACTERISTICS (Figures 5 and 6) (AVDD = DVDD = 3.3V ±5%, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIN to SCLK Setup tDS 50 ns DIN to SCLK Hold tDH 0ns SCLK to DOUT Valid tDO 70 ns CS Fall to DOUT Enable tDV CLOAD = 50pF 80 ns CS Rise to DOUT Disable tTR CLOAD = 50pF 80 ns CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0ns SCLK High Pulse Width tCH 120 ns SCLK Low Pulse Width tCL 120 ns SCLK Fall to SSTRB tSSTRB CLOAD = 50pF 80 ns CS Fall to SSTRB Enable tSDV CLOAD = 50pF, external clock mode 80 ns CS Rise to SSTRB Disable tSTR CLOAD = 50pF, external clock mode 80 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode 0 ns RST Pulse Width tRS 278 70 ns |
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