RoboClock
CY7B9945V
Document #: 38-07336 Rev. *D
Page 2 of 10
Pin Definitions
Pin
Name
I/O
Type
Description
34
FS
Input
Three-level
Input
Frequency Select. This input must be set according to the nominal frequency
(fNOM). See Table 1.
40,39,
36,37
REFA+, REFA-
REFB+, REFB-
Input
LVTTL/
LVDIFF
Reference Inputs. These inputs can operate as differential PECL or
single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input must be left open.
38
REFSEL
Input
LVTTL
Reference Select Input. The REFSEL input controls how the reference input
is configured. When LOW, it will use the REFA pair as the reference input.
When HIGH, it will use the REFB pair as the reference input. This input has
an internal pull-down.
42
FBK
Input
LVTTL
Feedback Input Clock. The PLL will operate such that the rising edges of
the reference and feedback signals are aligned in phase and frequency. This
pin is used to feedback the clock output QF to the phase detector.
28,18,
35,17,
2, 1
1F[0:3], 2F[0:1]
Input
3-level Input Output Phase Function Select. Each pair determines the phase of the
respective bank of outputs. See Table 3.
19,26
DIS[1:2]
Input
LVTTL
Output Disable. Each input controls the state of the respective output bank.
When HIGH, the output bank is disabled to “HOLD-OFF” or “High-Z” state;
the disable state is determined by MODE. When LOW, outputs 1Q[0:3] and
2Q[0:5] are enabled. See Table 5.
14,12,
13,3
[1:2]DS[0:1]
Input
3-level Input Output Divider Function Select. Each pair determines the divider ratio of
the respective bank of outputs. See Table 4.
29
FBF0
Input
3-level Input Feedback Output Phase Function Select. This input determines the phase
of the QF output. See Table 3.
50,51
FBDS[0:1]
Input
3-level Input Feedback Output Divider Function Select. This input determines the
divider ratio of the QF output. See Table 4.
48,46,
32,30,
5,7,8,10
, 20,22
1Q[0:3], 2Q[0:5]
Output
LVTTL
Clock Outputs with Adjustable Phases and fNOM Divide Ratios. The
output frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3]
and 2F[0:1], respectively. See Table 3 and Table 4.
44
QF
Output
LVTTL
Feedback Clock Output. This output is intended to be connected to the FBK
input. The output frequency and phase are determined by FBDS[0:1] and
FBF0, respectively. See Table 3 and 4.
52
LOCK
Output
LVTTL
PLL Lock Indicator. When HIGH, this output indicates the internal PLL is
locked to the reference signal. When LOW, it indicates that the PLL is
attempting to acquire lock
25
MODE
Input
3-level Input This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs will disable to high impedance state (High-Z). When
this input is LOW, the clock outputs will disable to HOLD-OFF mode. When
in MID, the device will enter factory test mode.
6,9,21,
31, 45,
47
VCCN
PWR
Power Supply for the Output Buffers
16,27,
41
VCCQ
PWR
Power Supply for the Internal Circuitry
4,11,15,
23,24,
33,43,4
9
GND
PWR
Device Ground
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