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CN8330EPFC Datasheet(PDF) 11 Page - Synaptics Incorporated. |
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CN8330EPFC Datasheet(HTML) 11 Page - Synaptics Incorporated. |
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11 / 101 page  100441E Conexant 1-1 1 1.0 Product Description The CN8330 is a frame synchronization, recovery, and signal generation circuit. Applications for digital terminals include digital cross-connect systems, customer premise multiplexers, channel extenders, network managers, PBXs, Switched Multimegabit Digital Service (SMDS) equipment, and monitor or test equipment. The integrated circuit features a High-Level Data Link Control (HDLC) formatter usable with or without DS3/E3 framing. The CN8330 framer is designed to meet the requirements of DS3 and E3 transmission and reception formats as per ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751 standards. Both the LAPD terminal data link and the Far End Alarm Control (FEAC) channel, as defined in T1.107a-1989, are supported. All maintenance features required by Bellcore TR-TSY-000009 and AT&T PUB 54014 are furnished. HDLC data transmission according to ITU-T standard Q.921 and ISO 3309-1984 is supported, as are SMDS standards prETS 300 214 and TR-TSV-000773. The framer provides framing recovery for M13, C-bit parity, and G.751 E3 formatted signals. The received data stream is available serially for unchannelized applications or for external decoding of the asynchronous multiplexed formats. The framing circuit has an average reframe time of less than 1 msec for DS3 signals and less than 250 µsec for E3 signals. A First In First Out (FIFO) buffer in the receive signal path can be enabled to reduce the jitter on the incoming data. The framer circuitry is capable of operating to 52 MHz, making it compatible with High-Speed Serial Interface (HSSI) signals or DS3 and E3 signals that are embedded in SONET STS-1 or SDH STM-1 carriers. The transmitter can process serial data from an external pin, or in byte- or nibble-oriented data format from the Payload Parallel Data Link (PPDL) data port. DS3 overhead bits or E3 Frame Alignment Signal (FAS) bits are automatically inserted. The parallel data can be formatted with idle flags, zero stuffing for transparency, and a selectable 16- or 32-bit Frame Check Sequence (FCS). Bytes or nibbles without HDLC formatting can also be transmitted. The transmitter also generates an Alarm Indication Signal (AIS), idle code, yellow alarm, and all-ones signals. DS3 C-bits (or E3 N-bits) can be inserted into the data stream from an external source. The circuit can be configured as a high-speed data formatter without inserting the CN8330 overhead bits. This allows the circuit to be used for data applications on communication links other than those requiring DS3 or E3 formatting. Data bytes can be formatted with HDLC flags and FCS bytes for transmission at any speed up to 52 MHz. |
Similar Part No. - CN8330EPFC |
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Similar Description - CN8330EPFC |
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