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AS4LC1M16E5-60TC Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part # AS4LC1M16E5-60TC
Description  3V 1M X 6 CMOS DRAM (EDO)
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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AS4LC1M16E5-60TC Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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AS4LC1M16E5
4/11/01
Alliance Semiconductor
4
DC electrical characteristics
Shaded areas indicate advance information.
Parameter
Symbol
Test conditions
-50
-60
Unit
Notes
Min
Max
Min
Max
Input leakage current
IIL
0V
≤ V
in ≤ VCC (max)
Pins not under test = 0V
-2
+2
-2
+2
µ
A
Output leakage current
IOL
DOUT disabled, 0V ≤ Vout ≤ VCC (max)
-2
+2
-2
+2
µ
A
Operating power
supply current
ICC1
RAS, UCAS, LCAS, Address cycling;
tRC=min
140
130
mA
4,5
TTL standby power
supply current
ICC2
RAS = UCAS = LCAS
≥ V
IH,
all other inputs at VIH or VIL
2.0
2.0
mA
Average power supply
current, RAS refresh
mode or CBR
ICC3
RAS cycling, UCAS = LCAS
≥ V
IH,
tRC = min of RAS low after XCAS low.
80
70
mA
4
EDO page mode average
power supply current
ICC4
RAS = VIL, UCAS or LCAS,
address cycling: tHPC = min
85
75
mA
4, 5
CMOS standby power
supply current
ICC5
RAS = UCAS = LCAS = VCC - 0.2V,
F = 0
1–1
mA
Output voltage
VOH
IOUT = -5.0 mA
2.4
–2.4
V
VOL
IOUT = 4.2 mA
0.4
0.4
V
CAS before RAS refresh
current
ICC6
RAS, UCAS or LCAS cycling, tRC = min
80
70
mA
Self refresh current
ICC7
RAS = UCAS = LCAS
≤ 0.2V,
WE = OE
≥ V
CC - 0.2V,
all other inputs at 0.2V or
VCC - 0.2V
0.5
0.5
mA


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