 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SAA7115 Datasheet(PDF) 73 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
SAA7115 Datasheet(HTML) 73 Page - NXP Semiconductors |
|
|
73 / 214 page  Confidential - NDA required page 73 Filename: SAA7115_Datasheet.fm Last edited by H. Lambers Philips Semiconductors CVIP2 Date: 10/23/01 CS-PD Hamburg Datasheet SAA7115 Version: 0.67 8.5.4.2 Data Packing (bit IMPAK (86H) and programming of the pulse generator via addr. F5H to FBH) To make use of the synthesized line locked PLL2 clock and to enable the use of the scaler for a wider application range, it is now possible to retain the output data of the scaler, until a scaled line can be output as a continuous data package. This is done via internal trigger pulses, one for each type of scaler output data (video from page A or B or sliced VBI data). The parameters PGHAPS (video page A), PGHBPS (video page B) and PGHCPS (sliced VBI data) are defining the delay related to the rising edge of the decoders HREF or of the synthesized HREF (generated by the internal pulse generator, see addr. F5H and F6H). The delay is counted in clock cycles and as a rough estimate for the internal buffering level you can take the following equation for the video data streaming. With num_buf_pix = number of buffered pixel, num_buf_lifo = number of pixel buffered in the internal line FIFO num_buf_fifo = number of pixel buffered in the output FIFO h_blanking = number of clock cycles during horizontal blanking = 288 (PAL), 276 (NTSC) sc_run_in = number of clock cycles for scaler running in = about 72 clock cycles for unscaled video num_buf_pix is about ~= (PGHAPS - h_blanking - sc_run_in) / 2 = num_buf_lifo + num_buf_fifo Where num_buf_lifo = 0 for num_buf_pix =< 64 and the maximum value of num_buf_lifo = 768dec num_buf_fifo = 64 for num_buf_pix > 64 For unscaled video a level around 1/2 of the buffer capacity (num_buf_lifo + num_buf_fifo = 832dec) is recommended. This leads to a PGHAPS value of about ~= 2 x 416 + h_blanking + sc_run_in = 1192 (PAL case) for the unscaled case. To be able to align the EAV sequences for different scales and regions, PGHBPS of page B is a separate parameter. The number of bytes per line and region defines, whether PGHBPS is to be programmed differently to PGHAPS. If all data types are to be mixed and a fixed SAV/EAV pattern is needed, the VBI slicer has to become the timing master for the data packing. To avoid timing shifts in the EAV pattern, the latest point of text line completion defines the earliest packing timing. This is about 48 clocks before rising edge of the decoders HREF. The slicer data need to be shifted to a position later than this point. The latest point in time is defined by the internal video skipping procedure (SLDOM[4] =’1’). Therefore the end of a video line (EAV) need to have a distance of (number of pixels per line) of clock cycles from the mentioned point of text line completion. Considering the PLL behaviour and for correct video skipping, the recommendation for this situation and EAV alignment for 720 pixel per line and PAL (=1728) is: 1728 - (48+56) - 720 - 1448 = -544 = 1184 >= PGHCPS >= 1728 - (48-20) = 1700 PGHAPS = PGHCPS - num_bytes_per_video_line + num_bytes_per_VBI_package = e.g. 1700 - 1448 + 56 = 308dec For other clock rates than 27 MHz, the mentioned values need to be scaled according to the clock relations, e.g. 24.545454 MHz would give 1560 - 94 - 640 - 1288 = -462 = 1098 >= PGHCPS >= 1560 - 25 = 1535 PGHAPS = e.g. 500 - 1288 + 51 = -737 = 823dec 8.5.5 DATA STREAM CODING AND REFERENCE SIGNAL GENERATION (SUBADDRESSES 84H, 85H AND 93H) As H and V reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. As an alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates. Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. So fixed propagation delays, in terms of clock cycles, related to the analog input cannot be defined. The data stream is accompanied by a data qualifier. ITU 656 like codes need to be activated by means of the bit ICODE set to ‘1’. The behaviour during non qualified clock cycles is defined by the bit INS80 [93H[6]]. With INS80 = ‘0’ the interface behaves like SAA7118/7114 and invalid data cycles are marked with code 00H. |
Similar Part No. - SAA7115 |
|
Similar Description - SAA7115 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
