MX98726 datasheet(11/55 Pages) MCNIX

Part #	MX98726

Description	SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

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Manufacturer	MCNIX [Macronix International]

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11

P/N:PM0555

REV. 0.9.8, FEB. 14, 2000

MX98726

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

GMAC Test Register A : TRA (Reg02h),R/W, default=00h

Bit

Symbol

Description

2.0

TEST

Test mode enable: Set to enable test modes defined by TMODE[2:0], default is reset

for normal operation.

2.1-2.3

TMODE[2:0]

Test Mode Select bits[2:0]: Reserved for GMAC's internal test, only meaningful when

TEST bit is set.

2.4

RWR

Receive Watchdog Release : When set, the receive watchdog is released 40 to 48 bit

times from the last carrier deassertion. When reset, the receive watchdog is re-

leased 16 to 24 bits times from the last carrier deassertion.

2.5

RWD

Receive Watchdog Disable : When set, the receive watchdog is disabled. When re-

set, receive carriers longer than 2560 bytes are guaranteed to cause the watchdog

timeout. Packets shorted than 2048 bytes are guaranteed to pass.

2.6

FC

Forced Collision : Set to force collision at every transmit packet, this bit works only in

internal FIFO loopback mode, i.e. LB0=1, LB1=0, to test excessive collision. Default

is reset.

2.7

SB

Start/Stop Backoff counter:When set, indicates internal backoff counter stops counting

when any carrier is detected. Counter resumed when carrier drops. When reset, the

internal backoff counter is not affected by carrier activity. Default is reset.

GMAC Test Register : TRB (Reg03h), R/W, default=00h

Bit

Symbol

Description

3.0

FKD*

Flaky Oscillator Disable: When set, indicates that the internal flaky oscillator is dis-

abled; pseudo random numbers are chosen instead of fully random numbers, used

for internal diagnostic purpose. Set to disable normal clocking scheme in timer's

test, set to enable timer test. Default is reset.

3.1

RDNCNTCB*

Reserved for test

3.2

RDNCNTSB*

Reserved for test

3.3

COLCNTCB*

Reserved for test

3.4

BFS0

Reserved for test

3.5

BKCNTLB*

Reserved for test

3.6

BFS1

Reserved for test

3.7

BFSTATUS

Reserved for test

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