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MB84VD23381HJ Datasheet(PDF) 3 Page - SPANSION |
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MB84VD23381HJ Datasheet(HTML) 3 Page - SPANSION |
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3 / 56 page  MBVD23381HJ-70 2 (Continued) —FLASH MEMORY • Simultaneous Read/Write operations (Dual Bank) • FlexBankTM*1 Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15) Bank B : 24 Mbit (64 KB × 48) Bank C : 24 Mbit (64 KB × 48) Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15) Two virtual Banks are chosen from the combination of four physical banks. Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program • Minimum 100,000 program/erase cycles • Sector erase architecture Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word. Any combination of sectors can be concurrently erased. It also supports full chip erase. • WP/ACC input pin At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM*2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM*2 Algorithms Automatically writes and verifies data at specified address • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, the device automatically switches itself to low power mode. • Low VCCf write inhibit ≤ 2.5 V • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Please refer to “MBM29DL64DH“ Datasheet in deteiled function (Continued) |
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