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LTC3770EG Datasheet(PDF) 8 Page - Linear Technology |
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LTC3770EG Datasheet(HTML) 8 Page - Linear Technology |
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8 / 24 page  8 LTC3770 3770f PI FU CTIO S (UH Package/G Package) to be the slave of two outputs, the VFB voltage of the master IC is reproduced by a resistor divider and applied to this pin. An internal 1.4µA soft start current is charging this pin during the soft-start phase. PLLFLTR (Pin 12/Pin 15): The Phase-Locked Loop’s Lowpass Filter is Tied to This Pin. The voltage at this pin defaults to 1.18V when the IC is not synchronized with an external clock at the PLLIN pin. PLLIN (Pin 13/Pin 16): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with a 50k resistor. VIN (Pin 14/Pin 17): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1µF to 1µF). VINSNS (Pin 15) UH Package: VIN Voltage Sense Input. Normally this pin is tied to VIN. However, in certain applications when the IC is powered from a separate supply, VINSNS is tied to the upper MOSFET supply to sense the VIN voltage. The pin is co-bonded with VIN in the SSOP package. ZVIN (Pin 16/Pin 18): Post-Package Zener-Trim Voltage Input. Under normal conditions this pin should always be connected to INTVCC. Z1 (Pin 17/Pin 19): Post-Package Zener-Trim Control. This pin is a multifunctional pin used in production for post-package trimming and tracking. Ground this pin under normal soft-start operation. Connecting this pin to INTVCC will turn off the soft-start current during tracking. Z2 (Pin 18/Pin 20): Post-Package Zener-Trim Control. This pin is used in production for Post-Package trimming. Ground this pin or tie to INTVCC under normal operation. INTVCC (Pin 19/Pin 21): Internal 5V Regulator Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 10µF low ESR tantalum or ceramic capacitor. DRVCC (Pin 20) UH Package Gate: Driver Voltage Input. Normally connected to the INTVCC regulated output. Do not exceed 7V at this pin. This pin is co-bonded to INTVCC internally in the SSOP package. BG (Pin 21/Pin 22): Bottom Gate Driver Output. This pin drives the gate of the bottom N-channel MOSFET between ground and INTVCC. PGND (Pin 22/Pin 23): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (–) terminal of CVCC and the (–) terminal of CIN. SENSE– (Pin 23) UH Package: Current Sense Comparator Input. The (–) input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET. This pin is co-bonded with PGND internally in the SSOP package. SENSE+ (Pin 24) UH Package: Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor. This pin is co-bonded with SW internally in the SSOP package. SW (Pin 25/Pin 24): Switch Node. The (–) terminal of the boot-strap capacitor CB connects here. This pin swings from a diode voltage drop below ground up to VIN. TG (Pin 26/Pin 25): Top Gate Drive Output. This pin drives the top N-channel MOSFET with a voltage swing equal to INTVCC, superimposed on the switch node voltage SW. BOOST (Pin 27/Pin 26): Boosted Floating Driver Supply. The (+) terminal of the boot-strap capacitor CB connects here. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. Z0 (Pin 28/Pin 27): Dead Time Control Input. Applying a DC voltage will vary the dead time between TG-Low and BG-High transition. Do not force a voltage higher than 5V on this pin. FCB (Pin 29/Pin 28): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. RUN (Pin 30/Pin 1): Run Control Input. A voltage above 1.5V turns on the IC. Forcing this pin below 1.5V shuts down the device. |
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