K4S641632E

CMOS SDRAM

Rev.0.2 Sept. 2001

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

3.3V

1200

Ω

870

Ω

Output

50pF

Vtt = 1.4V

50

Ω

Output

50pF

Z0 = 50

Ω

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

OPERATING AC PARAMETER

Notes :

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-50

-55

-60

-70

-75

-1H

-1L

Row active to row active delay

10

11

12

14

15

20

20

ns

1

RAS to CAS delay

15

16.5

18

20

20

20

20

ns

1

Row precharge time

15

16.5

18

20

20

20

20

ns

1

Row active time

38.5

38.5

42

49

45

50

50

ns

1

100

us

Row cycle time

55

55

60

68

65

70

70

ns

1

Last data in to row precharge

2

CLK

2,5

Last data in to active delay

2CLK

+15ns

2CLK

+16.5ns

2CLK

+18ns

2CLK

+20ns

2CLK

+20ns

2CLK

+20ns

2CLK

+20ns

-

5

Last data in to new col. address Delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

3

Number of valid output

data

CAS latency=3

2

ea

4

CAS latency=2

-

1

1. The DC/AC Test Output Load of K4S641632E-50/55/60 is 30pF.

2. The VDD condition of K4S641632E-50/55/60 is 3.135V~3.6V.

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.