6.42

6

IDT71V416VS, IDT71V416VL 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

ADDRESS

OE

CS

6478 drw 07

(3)

DATA

VALID

BHE, BLE

(3)

(3)

(2)

(2)

OUT

NOTES:

1. A write occurs during the overlap of a LOW

CS, LOW BHE or BLE, and a LOW WE.

2.

OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the

CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

NOTES:

1.

WE is HIGH for Read Cycle.

2. Address must be valid prior to or coincident with the later of

3. Transition is measured ±200mV from steady state.

ADDRESS

CS

6478 drw 08

(5)

(5)

(5)

(2)

WE

PREVIOUS DATA VALID

DATA VALID

(5)

(3)