PRELIMINARY
8K/16K x 9
Synchronous Dual-Port Static RAM
fax id: 5218
CY7C09159
CY7C09169
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 1997 - Revised June 5, 1998
51
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 2 Flow-Through/Pipelined devices
— 8K x 9 organization (CY7C09159)
— 16K x 9 organization (CY7C09169)
• 3 Modes
— Flow-Through
—Pipelined
—Burst
• Pipelined output mode on both ports allows fast
100-MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5/7.5/12 ns (max.)
• Low operating power
— Active= 200 mA (typical)
— Standby= 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
Note:
1.
A0–A12 for 8K; A0–A13 for 16K.
v
Logic Block Diagram
R/WL
CE0L
CE1L
OEL
FT/PipeL
I/O0L–I/O8L
Control
A0–A12/13L
CLKL
ADSL
CNTENL
CNTRSTL
R/WR
1
0
0/1
CE0R
CE1R
OER
1
0/1
0
FT/PipeR
I/O0R–I/O8R
I/O
Control
A0–A12/13R
CLKR
ADSR
CNTENR
CNTRSTR
1
0
0/1
1
0/1
0
I/O
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
9
9
[1]
[1]
13/14
13/14
For the most recent information, visit the Cypress web site at www.cypress.com
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
