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AMD27C64-90DCB Datasheet(PDF) 1 Page - Advanced Micro Devices |
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AMD27C64-90DCB Datasheet(HTML) 1 Page - Advanced Micro Devices |
1 / 11 page Publication# 11419 Rev. D Amendment /0 Issue Date: May 1995 2-10 Advanced Micro Devices Am27C64 64 Kilobit (8,192 x 8-Bit) CMOS EPROM FINAL DISTINCTIVE CHARACTERISTICS s Fast access time — 45 ns s Low power consumption — 20 µA typical CMOS standby current s JEDEC-approved pinout s Single +5 V power supply s ±10% power supply tolerance available s 100% FlashriteTM programming — Typical programming time of 1 second s Latch-up protected to 100 mA from –1 V to VCC + 1 V s High noise immunity s Versatile features for simple interfacing — Both CMOS and TTL input/output compatibility — Two line control functions s Standard 28-pin DIP, PDIP, and 32-pin PLCC packages GENERAL DESCRIPTION The Am27C64 is a 64-Kbit ultraviolet erasable program- mable read-only memory. It is organized as 8K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in win- dowed ceramic DIP packages as well as plastic one time programmable (OTP) PDIP, and PLCC packages. Typically, any byte can be accessed in less than 45 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27C64 offers separate Output Enable ( OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 80 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C64 supports AMD’s Flashrite programming algorithm (100 µs pulses) resulting in a typical programming time of 1 second. BLOCK DIAGRAM VCC VSS Output Enable Chip Enable and Prog Logic Y Decoder X Decoder CE OE Output Buffers Y Gating 65,538 Bit Cell Matrix A0–A12 Address Inputs Data Outputs DQ0–DQ7 11419D-1 VPP PGM |
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