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AD8091ART-REEL7 Datasheet(PDF) 5 Page - Analog Devices |
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AD8091ART-REEL7 Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page –5– AD8091/AD8092 REV. A ABSOLUTE MAXIMUM RATINGS * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . ±V S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±2.5 V Output Short Circuit Duration . . . . . . . . . . . . . See Figure 1 Storage Temperature Range . . . . . . . . . . . –65 °C to +125°C Operating Temperature Range . . . . . . . . . . . –40 °C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8091/AD8092 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately 150 °C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8091/AD8092. Exceeding a junction temperature of 175 °C for an extended period of time can result in changes in the silicon devices, potentially causing failure. The still-air thermal properties of the package ( JA), ambient temperature (TA), and the total power dissipated in the package (PD) can be used to determine the junction temperature of the die. The junction temperature can be calculated as follows: TT P AD A JJ =+ × () θ The power dissipated in the package (PD) is the sum of the quies- cent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS /2 IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = quiescent power + (total drive power – load power) PV I VV R V R SS S OUT L OUT L D =× ()+× 2 2 – RMS output voltages should be considered. (If RL is referenced to VS–, as in single-supply operation, then the total drive power is VS IOUT.) If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS /4 for RL to midsupply: PV I V R DS S S L =× ()+ 4 2 (In single-supply operation with RL referenced to VS–, worst case is VOUT = VS /2.) Airflow will increase heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the JA. Care must be taken to minimize parasitic capacitances at the input leads of high-speed op amps as discussed in the board layout section. Figure 1 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC-8 (125 °C/W), SOT23-5 (180 °C/W), and µSOIC-8 (150°C/W) packages on a JEDEC standard four-layer board. AMBIENT TEMPERATURE – C 2.0 1.0 0 –30 1.5 0.5 80 40 50 10 –10 30 TJ = 150 C SOIC-8 SOIC-8 –20 0 20 60 70 90 SOT23-5 –40 Figure 1. Maximum Power Dissipation vs. Temperature for a Four-Layer Board |
Similar Part No. - AD8091ART-REEL7 |
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Similar Description - AD8091ART-REEL7 |
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