3D7205

MONOLITHIC 5-TAP

FIXED DELAY LINE

(SERIES 3D7205)

FEATURES

PACKAGES

1

2

3

4

8

7

6

5

IN

O2

O4

GND

VDD

O1

O3

O5

3D7205Z

SOIC

(150 Mil)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IN

N/C

N/C

O2

N/C

O4

N/C

GND

VDD

N/C

N/C

O1

N/C

O3

N/C

O5

3D7205S SOL

(300 Mil)

8

7

6

5

1

2

3

4

IN

O2

O4

GND

VDD

O1

O3

O5

3D7205M DIP

3D7205H Gull-Wing

14

13

12

11

10

9

8

1

2

3

4

5

6

7

IN

N/C

N/C

O2

N/C

O4

GND

VDD

N/C

O1

N/C

O3

N/C

O5

3D7205

DIP

3D7205G Gull-Wing

3D7205K Unused pins

removed

•

All-silicon, low-power CMOS

technology

•

TTL/CMOS compatible

inputs and outputs

•

Vapor phase, IR and wave

solderable

•

Auto-insertable (DIP pkg.)

•

Low ground bounce noise

•

Leading- and trailing-edge accuracy

•

Delay range: 8 through 500ns

•

Delay tolerance: 5% or 2ns

•

Temperature stability:

±3% typical (0C-70C)

•

Vdd stability:

±2% typical (4.75V-5.25V)

•

Minimum input pulse width: 20% of total delay

•

14-pin DIP and 16-pin SOIC available as drop-in

For mechanical dimensions, click

here.

For package marking details, click

here.

replacements for hybrid delay lines

FUNCTIONAL DESCRIPTION

The 3D7205 5-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 8.0ns through 100ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D7205 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

The all-CMOS 3D7205 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-

insertable DIP and a space saving surface mount 8-pin SOIC.

PIN DESCRIPTIONS

IN

Delay Line Input

O1

Tap 1 Output (20%)

O2

Tap 2 Output (40%)

O3

Tap 3 Output (60%)

O4

Tap 4 Output (80%)

O5

Tap 5 Output (100%)

VDD +5 Volts

GND Ground

N/C

No Connection

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

TOLERANCES

INPUT RESTRICTIONS

DIP-8

3D7205M

3D7205H

SOIC-8

3D7205Z

DIP-14

3D7205

3D7205

G

3D7205K

SOIC-16

3D7205S

TOTAL

DELAY (ns)

TAP-TAP

DELAY

(ns)

Max

Operating

Frequency

Absolute

Max

Oper. Freq.

Min

Operating

Pulse Width

Absolute

Min

Oper. P.W.

-8

-8

-8

-8

40.0

± 2.0

8.0

± 1.5

9.52 MHz

71.4 MHz

52.5 ns

7.0 ns

-10

-10

-10

-10

50.0

± 2.5

10.0

± 2.0

6.67 MHz

50.0 MHz

75.0 ns

10.0 ns

-15

-15

-15

-15

75.0

± 3.8

15.0

± 2.3

4.44 MHz

33.3 MHz

113 ns

15.0 ns

-20

-20

-20

-20

100

± 5.0

20.0

± 2.5

3.33 MHz

25.0 MHz

150 ns

20.0 ns

-25

-25

-25

-25

125

± 6.3

25.0

± 2.5

2.66 MHz

20.0 MHz

188 ns

25.0 ns

-30

-30

-30

-30

150

± 7.5

30.0

± 3.0

2.22 MHz

16.7 MHz

225 ns

30.0 ns

-50

-50

-50

-50

250

± 12.5

50.0

± 5.0

1.33 MHz

10.0 MHz

375 ns

50.0 ns

-75

-75

-75

-75

375

± 18.8

75.0

± 7.5

0.89 MHz

6.67 MHz

563 ns

75.0 ns

-100

-100

-100

-100

500

± 25.0

100

± 10.0

0.67 MHz

5.00 MHz

750 ns

100.0 ns

Doc #96007

DATA DELAY DEVICES, INC.

1

12/2/96

3 Mt. Prospect Ave. Clifton, NJ 07013